1. Field of the Invention
The present invention relates generally to varactor bank switching, and in particular to configuration of varactor bank switches.
2. Background Information
Varactor banks are applied in LC-tank voltage controlled oscillators (VCO) to perform a coarse tuning of the oscillation frequency. LC-tank oscillators are typically used in communication systems, such as in generating high frequency oscillator signals in microwave or radio frequency apparatus. A typical LC-tank circuit includes inductors (L) and capacitors (C) configured in a circuit such that the inductors and capacitors oscillate because of current or voltage exchange between inductors and capacitors at a specified frequency. To achieve a high Cmax/Cmin-ratio, switches are used in the varactor bank, where Cmax and Cmin denote the maximum and minimum capacitance values of the varactor at e.g., a logical low and high biasing voltage. If the process technology provides varactors with an inherently high variability of the capacitance, i.e., a high Cmax/Cmin-ratio, the variable capacitors in the varactor bank can directly be driven by a control signal (i.e., logical low for Cmax and logical high for Cmin) and dedicated switches within the varactor banks are not necessary. This invention, however, assumes that the process technology available (e.g. a typical digital CMOS process for mainstream applications) does only provide varactors with a low or medium Cmax/Cmin-ratio, which requires the application of switches to maximize the overall Cmax/Cmin-ratio of the varactor bank.
If the varactor bank switches in the off-state become conductive during certain fractions of the oscillation period, the phase noise of the LC-tank VCO may significantly degrade. FIG. 1 shows a schematic of a conventional varactor bank circuit, illustrating the problem that the varactor bank switch in the off-state becomes conductive during certain fractions of the oscillation period. The varactor bank is part of a tuning capacitance. The circuit in FIG. 1 includes two MOSFET varactors M4, M5 whose diffusion-side terminals are connected to the source and drain nodes of a NMOS FET switch M1. In this configuration the source and drain potentials of M1 are floating in the on-state of the varactor bank. To prevent uncontrolled variations of the potentials at these nodes, two additional MOSFET switches M2 and M3 are connected between ground and the drain and source nodes of M1. All of the transistors M1-M3 are either turned on if the varactor bank is enabled or turned off if the varactor bank is disabled. M1 is much bigger than M2 and M3 because it has to provide a low impedance path for the oscillator signal propagating from M5 to M4 and vice versa. M2 and M3 are only used to provide a high impedance dc path such as to appropriately bias the source and drain nodes of M1.
A disadvantage of the circuit in FIG. 1 is that the switch transistor M1 can get turned on in the off-state, if the source potential becomes sufficiently negative such that Vgs of M1 is higher than the threshold voltage Vth despite the gate potential of M1 is 0V (i.e., the control signal Vctrl is 0V.This situation typically occurs in the areas around the peak values of the negative-going half-waves of the oscillation signal and the described effect increases the larger the signal swing becomes. This phenomenon occurs in both half-waves of the oscillation period because the source and drain nodes exchange their roles in this symmetrical varactor bank design with respect to the definition of the half-wave directions. During those fractions of the oscillation period where Vgs>Vth holds true, the switch transistor M1 becomes conductive despite the fact that it should remain turned off. The time intervals where M1 becomes conductive are indicated by waveforms in FIG. 1 as horizontal arrows below the actual oscillation signal curve.
The impact of these partially conductive states on the phase noise performance is shown in Table I below, which summarizes certain measured results of a VCO design in 45 mn CMOS technology that applies the varactor bank switching of FIG. 1. It is clear that the phase noise performance in the off-state of the varactor banks is worse by at least 12 dBc/Hz compared to the case where the varactor bank switches are turned on. A phase noise degradation of more than 12 dBc/Hz can be regarded as being quite significant in high-Q VCO design.
TABLE Iall varactorsphase noise atbanks1 MHz offsetlow frequencyall secondary coilsoff−114.2 dBc/Hzrangeopenon−121.6 dBc/Hzmid frequencyouter secondaryoff−107.5 dBc/Hzrangecoil closedon−119.4 dBc/Hzhigh frequencyouter and inneroff−101.5 dBc/Hzrangesecondary coils closedon−119.4 dBc/HzMeasurement results of implemented prior art circuit in a 45 nm CMOS technology CMOS SOI12S. The phase noise degradation owing to the partially conductive switches in the off-state of the varactor banks is more than 12 dBc/Hz.Note that the first two columns refer to the additionally implemented inductor switching, which is, however, not directly related to the discussed problem of varactor bank switching.